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112

8272E–AVR–04/2013

ATmega164A/PA/324A/PA/644A/PA/1284/P

Figure 16-1. 16-bit Timer/Counter block diagram

(Note:).

Note:

Refer to Figure 1-1 on page 2 and ”Alternate Port Functions” on page 77 for Timer/Counter1 pin

placement and description.

16.2.1

Registers

The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg-

ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16-

bit registers. These procedures are described in the section ”Accessing 16-bit Registers” on

page 113. The Timer/Counter Control Registers (TCCRnA/B/C) are 8-bit registers and have no

CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all

visible in the Timer Interrupt Flag Register (TIFRn). All interrupts are individually masked with

the Timer Interrupt Mask Register (TIMSKn). TIFRn and TIMSKn are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the Tn pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk

Tn).

The double buffered Output Compare Registers (OCRnA/B/C) are compared with the

Timer/Counter value at all time. The result of the compare can be used by the Waveform Gener-

ator to generate a PWM or variable frequency output on the Output Compare pin (OCnA/B/C).

Clock Select

Timer/Counter

ATA

OCRnA

OCRnB

ICRn

TCNTn

Waveform

Generation

Waveform

Generation

OCnA

OCnB

Noise

Canceler

ICPn

Fixed

TOP

Values

Edge

Detector

Control Logic

= 0

TOP

BOTTOM

Count

Clear

Direction

TOVn

(Int.Req.)

OCnA

(Int.Req.)

OCnB

(Int.Req.)

ICFn (Int.Req.)

TCCRnA

TCCRnB

( From Analog

Comparator Ouput )

Edge

Detector

( From Prescaler )

clk

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